FDMC2514SDC n-channel dual cool tm powertrench ? syncfet tm ?2010 fairchild semiconductor corporation FDMC2514SDC rev.c2 www.fairchildsemi.com 1 october 2010 FDMC2514SDC n-channel dual cool tm powertrench ? syncfet tm 25 v, 40 a, 3.5 m features ? dual cool tm top side cooling pqfn package ? max r ds(on) = 3.5 m at v gs = 10 v, i d = 22.5 a ? max r ds(on) = 4.7 m at v gs = 4.5 v, i d = 18 a ? high performance technology for extremely low r ds(on) ? syncfet schottky body diode ? rohs compliant general description this n-channel mosfet is produced using fairchild semiconductor?s advanced powertrench ? process. advancements in both silicon and dual cool tm package technologies have been combined to offer the lowest r ds(on) while maintaining excellent swit ching performance by extremely low junction-to-ambient thermal re sistance. this device has the added benefit of an efficient monolithic schottky body diode. applications ? synchronous rectifier for dc/dc converters ? telecom secondary side rectification ? high end server/workstation vcore low side mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 25 v v gs gate to source voltage (note 4) 20 v i d drain current -continuous (package limited) t c = 25 c 40 a -continuous (silicon limited) t c = 25 c 106 -continuous t a = 25 c (note 1a) 24 -pulsed 200 e as single pulse avalanche energy (note 3) 84 mj dv/dt peak diode recovery dv/dt (note 5) 2.0 v/ns p d power dissipation t c = 25 c 60 w power dissipation t a = 25 c (note 1a) 3.0 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case (top source) 5.8 c/w r jc thermal resistance, junction to case (bottom drain) 2.1 r ja thermal resistance, junction to ambient (note 1a) 42 r ja thermal resistance, junction to ambient (note 1b) 105 r ja thermal resistance, junction to ambient (note 1i) 17 r ja thermal resistance, junction to ambient (note 1j) 26 r ja thermal resistance, junction to ambient (note 1k) 12 device marking device package reel size tape width quantity 2514s FDMC2514SDC dual cool tm power 33 13?? 12 mm 3000 units top power 33 bottom d d d d g s s s pin 1 4 3 2 1 5 6 7 8 s s s g d d d d
FDMC2514SDC n-channel dual cool tm powertrench ? syncfet tm www.fairchildsemi.com 2 ?2010 fairchild semiconductor corporation FDMC2514SDC rev.c2 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 1 ma, v gs = 0 v 25 v bv dss t j breakdown voltage temperature coefficient i d = 10 ma, referenced to 25 c 21 mv/c i dss zero gate voltage drain current v ds = 20 v, v gs = 0 v 500 a i gss gate to source leakage current, forward v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 1 ma 1.2 1.7 3.0 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 10 ma, referenced to 25 c -5 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 22.5 a 2.5 3.5 m v gs = 4.5 v, i d = 18 a 3.6 4.7 v gs = 10 v, i d = 22.5 a, t j = 125 c 3.5 4.5 g fs forward transconductance v ds = 5 v, i d = 22.5 a 122 s c iss input capacitance v ds = 13 v, v gs = 0 v, f = 1 mhz 2031 2705 pf c oss output capacitance 596 795 pf c rss reverse transfer capacitance 134 205 pf r g gate resistance 1.1 2.4 t d(on) turn-on delay time v dd = 13 v, i d = 22.5 a, v gs = 10 v, r gen = 6 11 22 ns t r rise time 3.6 10 ns t d(off) turn-off delay time 26 41 ns t f fall time 310ns q g total gate charge v gs = 0 v to 10 v v dd = 13 v, i d = 22.5 a 31 44 nc q g total gate charge v gs = 0 v to 4.5 v 14 20 nc q gs gate to source gate charge 6.5 nc q gd gate to drain ?miller? charge 3.9 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 22.5 a (note 2) 0.79 1.2 v v gs = 0 v, i s = 2 a (note 2) 0.47 0.8 t rr reverse recovery time i f = 22.5 a, di/dt = 300 a/ s 24 39 ns q rr reverse recovery charge 19 34 nc
FDMC2514SDC n-channel dual cool tm powertrench ? syncfet tm www.fairchildsemi.com 3 ?2010 fairchild semiconductor corporation FDMC2514SDC rev.c2 thermal characteristics r jc thermal resistance, junction to case (top source) 5.8 c/w r jc thermal resistance, junction to case (bottom drain) 2.1 r ja thermal resistance, junction to ambient (note 1a) 42 r ja thermal resistance, junction to ambient (note 1b) 105 r ja thermal resistance, junction to ambient (note 1c) 29 r ja thermal resistance, junction to ambient (note 1d) 40 r ja thermal resistance, junction to ambient (note 1e) 19 r ja thermal resistance, junction to ambient (note 1f) 23 r ja thermal resistance, junction to ambient (note 1g) 30 r ja thermal resistance, junction to ambient (note 1h) 79 r ja thermal resistance, junction to ambient (note 1i) 17 r ja thermal resistance, junction to ambient (note 1j) 26 r ja thermal resistance, junction to ambient (note 1k) 12 r ja thermal resistance, junction to ambient (note 1l) 16 notes: 1. r ja is determined with the device mounted on a fr-4 board using a specified pad of 2 oz copper as shown below. r jc is guaranteed by design while r ca is determined by the user's board design. c. still air, 20.9x10.4x12.7mm aluminum heat sink, 1 in 2 pad of 2 oz copper d. still air, 20.9x10.4x12.7mm aluminum heat sink, minimum pad of 2 oz copper e. still air, 45.2x41.4x11.7mm aavid thermalloy part # 10-l41b-11 heat sink, 1 in 2 pad of 2 oz copper f. still air, 45.2x41.4x11.7mm aavid thermalloy part # 10-l41b-11 heat sink, minimum pad of 2 oz copper g. 200fpm airflow, no heat sink,1 in 2 pad of 2 oz copper h. 200fpm airflow, no heat sink, minimum pad of 2 oz copper i. 200fpm airflow, 20.9x10.4x12.7mm aluminum heat sink, 1 in 2 pad of 2 oz copper j. 200fpm airflow, 20.9x10.4x12.7mm aluminum heat sink, minimum pad of 2 oz copper k. 200fpm airflow, 45.2x41.4x11.7mm aavid thermalloy part # 10-l41b-11 heat sink, 1 in 2 pad of 2 oz copper l. 200fpm airflow, 45.2x41.4x11.7mm aavid thermalloy part # 10-l41b-11 heat sink, minimum pad of 2 oz copper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. e as of 84 mj is based on starting t j = 25 c, l = 1 mh, i as = 13 a, v dd = 23 v, v gs = 10 v. 100% test at l = 0.3 mh, i as = 20 a. 4. as an n-ch device, the negative vgs rating is for low duty cycle pulse ocurrence only. no continuous rating is implied. 5. i sd 22.5 a, di/dt 200 a/ s, v dd bv dss , starting t j = 25 o c. a. 42 c/w when mounted on a 1 in 2 pad of 2 oz copper b. 105 c/w when mounted on a minimum pad of 2 oz copper
FDMC2514SDC n-channel dual cool tm powertrench ? syncfet tm www.fairchildsemi.com 4 ?2010 fairchild semiconductor corporation FDMC2514SDC rev.c2 typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 30 60 90 120 v gs = 3.5 v v gs = 4.5 v v gs = 10 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 2.5 v v gs = 3 v i d , drain current (a) v ds , drain to source voltage (v) on-region characteristics figure 2. 0 306090120 0 1 2 3 4 5 6 7 8 v gs = 4.5 v v gs = 2.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 3 v v gs = 3.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 i d = 22.5 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 0 2 4 6 8 10 12 t j = 125 o c i d = 22.5 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 30 60 90 120 t j = 125 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 200 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMC2514SDC n-channel dual cool tm powertrench ? syncfet tm www.fairchildsemi.com 5 ?2010 fairchild semiconductor corporation FDMC2514SDC rev.c2 figure 7. 0 4 8 121620242832 0 2 4 6 8 10 i d = 22.5 a v dd = 16 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 13 v gate charge characteristics figure 8. 0.1 1 10 60 100 1000 3000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 30 c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 10 100 1 10 30 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability f i g u r e 1 0 . m a x i m u m c o n t i n u o u s d r a i n cu rrent vs case temperature 25 50 75 100 125 150 0 40 80 120 limited by package v gs = 4.5 v r t jc = 2.1 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) figure 11. 0.01 0.1 1 10 100 0.01 0.1 1 10 100 300 1ms 10 ms 100 ms dc 10 s 1 s 100 us i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 105 o c/w t a = 25 o c f o r w a r d b i a s s a f e operating area f i g u r e 1 2 . s i n g l e p u l s e m a x i m u m po wer dissipation 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 1000 2000 p (pk) , peak transient power (w) single pulse r t ja = 105 o c/w t a = 25 o c t, pulse width (sec) typical characteristics t j = 25 c unless otherwise noted
FDMC2514SDC n-channel dual cool tm powertrench ? syncfet tm www.fairchildsemi.com 6 ?2010 fairchild semiconductor corporation FDMC2514SDC rev.c2 figure 13. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.0005 0.001 0.01 0.1 1 single pulse r t ja = 105 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25 c unless otherwise noted
FDMC2514SDC n-channel dual cool tm powertrench ? syncfet tm www.fairchildsemi.com 7 ?2010 fairchild semiconductor corporation FDMC2514SDC rev.c2 syncfet schottky body diode characteristics fairchild?s syncfet process emb eds a schottky diode in parallel with powertrench mosfet. th is diode exhibits similar characteristics to a discrete exte rnal schottky diode in parallel with a mosfet. figure 13 shows the reverse recovery characteristic of the FDMC2514SDC. schottky barrier diodes exhibit significant leakage at high tem - perature and high reverse voltage. this will increase the power in the device. typical char acteristics (continued) figure 14. FDMC2514SDC syncfet body diode reverse recovery characteristic figure 15. syncfet body diode reverse leakage versus drain-source voltage 0 5 10 15 20 25 10 -6 10 -5 10 -4 10 -3 10 -2 t j = 125 o c t j = 100 o c t j = 25 o c i dss , reverse leakage current (a) v ds , reverse voltage (v) 0 50 100 150 200 -5 0 5 10 15 20 25 di/dt = 300 a/ s current (a) time (ns)
FDMC2514SDC n-channel dual cool tm powertrench ? syncfet tm www.fairchildsemi.com 8 ?2010 fairchild semiconductor corporation FDMC2514SDC rev.c2 dimensional outline and pad layout
www.fairchildsemi.com 9 FDMC2514SDC n-channel dual cool tm powertrench ? syncfet tm ?2010 fairchild semiconductor corporation FDMC2514SDC rev.c2 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairch ild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform wh en properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably ex pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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